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| this is information on a product in full production. june 2014 docid023719 rev 3 1/46 lis3de mems digital output motion sensor: ultra-low-power high-performance 3-axis "nano" accelerometer datasheet - production data features ? wide supply voltage, 1.71 v to 3.6 v ? independent io supply (1.8 v) and supply voltage compatible ? ultra-low-power mode consumption down to 2 a ?? 2 g /4 g / ? 8 g / ? 16 g dynamically selectable full scales ? i 2 c/spi digital output interface ? 8-bit data output ? 2 independent programmable interrupt generators for free-fall and motion detection ? 6d/4d orientation detection ? ?sleep-to-wake? and ?return-to-sleep? functions ? free-fall detection ? motion detection ? embedded temperature sensor ? embedded self-test ? embedded fifo ? 10000 g high shock survivability ? ecopack ? , rohs and ?green? compliant applications ? motion-activated functions ? free-fall detection ? click/double-click recognition ? intelligent power saving for handheld devices ? pedometers ? display orientation ? gaming and virtual reality input devices ? impact recognition and logging ? vibration monitoring and compensation description the lis3de is an ultra-low-power high- performance 3-axis linear accelerometer belonging to the ?nano? family, with digital i 2 c/spi serial interface standard output. the device features ultra-low-power operational modes that allow advanced power saving and smart embedded functions. the lis3de has dynamically user-selectable full scales of ? 2 g / ? 4 g / ? 8 g / ? 16 g and is capable of measuring accelerations with output data rates from 1 hz to 5 khz. the self-test capability allows the user to check the functioning of the sensor in the final application. the device may be configured to generate interrupt signals by two independent inertial wakeup/free-fall events as well as by the position of the device itself. thresholds and the timing of interrupt generators are programmable by the end user on the fly. the lis3de has an integrated 32-level first-in, first-out (fifo) buffer allowing the user to store data in order to limit intervention by the host processor. the lis3de is available in a small thin plastic land grid array package (lga) and it is guaranteed to operate over an extended temperature range from -40 c to +85 c. lga-16 (3x3x1 mm) table 1. device summary order codes temp. range [ ? c] package packaging lis3de -40 to +85 lga-16 tray LIS3DETR -40 to +85 lga-16 tape and reel www.st.com
contents lis3de 2/46 docid023719 rev 3 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.2 i 2 c - inter-ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.1 normal mode, low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.3 6d / 4d orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.4 sleep-to-wake and return-to-sleep functions . . . . . . . . . . . . . . . . . . . . . 16 3.3 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7 auxiliary adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 docid023719 rev 3 3/46 lis3de contents 46 5.1 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.4 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.5 retrieving data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 status_reg_aux (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 out_adc1_l (08h), out_adc1_h (09h) . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 out_adc2_l (0ah), out_adc2_h (0bh) . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 out_adc3_l (0ch), out_adc3_h (0dh) . . . . . . . . . . . . . . . . . . . . . . 29 8.5 int_counter_reg (0eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.6 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7 temp_cfg_reg (1fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.8 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.9 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.10 ctrl_reg3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.11 ctrl_reg4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.12 ctrl_reg5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.13 ctrl_reg6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.14 reference (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.15 status_reg2 (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.16 out_x (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.17 out_y (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 contents lis3de 4/46 docid023719 rev 3 8.18 out_z (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.19 fifo_ctrl_reg (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.20 fifo_src_reg (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.21 ig1_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.22 ig1_source (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.23 ig1_ths (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.24 ig1_duration (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.25 ig2_cfg (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.26 ig2_source (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.27 ig2_ths (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.28 ig2_duration (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.29 click_cfg (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.30 click_src (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.31 click_ths (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.32 time_limit (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.33 time_latency (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.34 time_window (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.35 act_ths (3eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.36 act_dur (3fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 docid023719 rev 3 5/46 lis3de list of tables 46 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 23 table 16. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 23 table 17. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. status_reg_aux register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 table 19. status_reg_aux register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 20. int_counter_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 21. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 22. temp_cfg_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 23. temp_cfg_reg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24. ctrl_reg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 25. ctrl_reg1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 table 26. data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 27. ctrl_reg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 28. ctrl_reg2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 29. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 30. ctrl_reg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 31. ctrl_reg3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 table 32. ctrl_reg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 33. ctrl_reg4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 table 34. self-test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 35. ctrl_reg5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 36. ctrl_reg5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 table 37. ctrl_reg6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 38. ctrl_reg6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 table 39. reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 40. reference register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 41. status_reg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 42. status_reg2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 43. fifo_ctrl_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 44. fifo_ctrl_reg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 45. fifo mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 46. fifo_src_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 47. fifo_src_reg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 48. ig1_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 list of tables lis3de 6/46 docid023719 rev 3 table 49. ig1_cfg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 50. interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 51. ig1_source register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 52. ig1_source register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 53. ig1_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 54. ig1_ths register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 55. ig1_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 56. ig1_duration register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 57. ig2_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 58. ig2_cfg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 59. interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 60. ig2_source register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 61. ig2_source register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 62. ig2_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 63. ig2_ths register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 64. ig2_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 65. ig2_duration register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 66. click_cfg register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 67. click_cfg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 68. click_src register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 69. click_src register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 70. click_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 71. click_ths register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 72. time_limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 73. time_limit register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 74. time_latency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 75. time_latency register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 76. time_window register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 77. time_window register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 78. act_ths register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 79. act_ths register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 80. act_dur register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 81. act_dur register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 82. lga-16: mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 83. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 docid023719 rev 3 7/46 lis3de list of figures 46 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. i 2 c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. lis3de electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. multiple byte spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. lga-16: drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 block diagram and pin description lis3de 8/46 docid023719 rev 3 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. pin connections charge amplifier y+ z+ y- z- a x+ x- i2c spi cs scl/spc sda/sdi/sdo sdo/sa0 control logic & interrupt gen. int 1 clock trimming circuits reference self test control a/d converter 1 int 2 mux 32 level fifo adc1 - adc input1 adc2 - adc input2 adc3 - adc input3 a/d converter 2 logic temperature sensor am14755v1 (top view) direction of the detectable accelerations 1 5 9 13 (bottom view) y 1 x z pin 1 indicator vdd_io nc nc sc l/spc gnd sda/sdi/sdo cs sdo/sa0 adc3 gnd int1 res int2 adc1 vdd adc2 am14756v1 docid023719 rev 3 9/46 lis3de block diagram and pin description 46 table 2. pin description pin# name function 1 vdd_io power supply for i/o pins 2 nc not connected 3 nc not connected 4 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 5 gnd 0 v supply 6 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 7 sdo sa0 spi serial data output (sdo) i 2 c least significant bit of the device address (sa0) 8cs spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 9 int2 interrupt 2 10 res connect to gnd 11 int1 interrupt 1 12 gnd 0 v supply 13 adc3 analog-to-digital converter input 3 14 vdd power supply 15 adc2 analog-to-digital converter input 2 16 adc1 analog-to-digital converter input 1 mechanical and electrical specifications lis3de 10/46 docid023719 rev 3 2 mechanical and electrical specifications 2.1 mechanical characteristics vdd = 2.5 v, t = 25 c unless otherwise noted (a) . a. the product is factory calibrated at 2.5 v. the operational power supply range is from 1.71 v to 3.6 v. table 3. mechanical characteristics symbol parameter test conditions min. typ. (1) max. unit fs measurement range (2) fs bit set to 00 2.0 g fs bit set to 01 4.0 fs bit set to 10 8.0 fs bit set to 11 16.0 so sensitivity fs bit set to 00 15.6 m g /digit fs bit set to 01 31.2 m g /digit fs bit set to 10 62.5 m g /digit fs bit set to 11 187.5 m g /digit tcso sensitivity change vs. temperature fs bit set to 00 0.05 %/c tyoff typical zero- g level offset accuracy (3)(4) fs bit set to 00 100 m g tcoff zero- g level change vs. temperature max. delta from 25 c 0.8 m g /c vst self-test output change (5)(6)(7) fs bit set to 00 x-axis 50 1800 m g fs bit set to 00 y-axis 50 1800 m g fs bit set to 00 z-axis 50 1800 m g t op operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. verified by wafer level test and measurement of initial offset and sensitivity. 3. typical zero- g level offset value after msl3 preconditioning. 4. offset can be eliminated by enabling the built-in high-pass filter. 5. the sign of the ?self-test output change? is defined by ctrl_reg4 st sign bits, for all axes. 6. the ?self-test output change? is defined as the absolute value of: output[lsb] (ctrl_reg4 st1, st0 bits=01) - output[lsb] (ctrl_reg4 st1, st0 bits=00) 7. output data reaches 99% of final value after 1ms+1/odr when enabling the self-test mode, due to device filtering. docid023719 rev 3 11/46 lis3de mechanical and electrical specifications 46 2.2 temperature sensor characteristics vdd = 2.5 v, t = 25 c unless otherwise noted (b) . 2.3 electrical characteristics vdd = 2.5 v, t = 25 c unless otherwise noted (c) . b. the product is factory calibrated at 2.5 v. table 4. temperature sensor characteristics symbol parameter test condition min. typ. (1) max. unit tsdr temperature sensor output change vs. temperature 1 digit/c (2) todr temperature refresh rate odr hz t op operating temperature range -40 +85 c 1. typical specifications are not guaranteed. temperature sensor operation is guaranteed in the range 2 v - 3.6 v. 2. 8-bit resolution. c. the product is factory calibrated at 2.5 v. the operational power supply range is from 1.71 v to 3.6 v. table 5. electrical characteristics symbol parameter test conditions min. typ. (1) max. unit vdd supply voltage 1.71 2.5 3.6 v vdd_io i/o pins supply voltage (2) 1.71 vdd+0.1 v idd current consumption in normal mode 50 hz odr 11 a idd current consumption in normal mode 1 hz odr 2 a iddlp current consumption in low-power mode 50 hz odr 6 a iddpdn current consumption in power-down mode 0.5 a vih digital high-level input voltage 0.8*vdd_io v vil digital low-level input voltage 0.2*vdd_io v voh high-level output voltage 0.9*vdd_io v vol low-level output voltage 0.1*vdd_io v bw system bandwidth (3) odr/2 hz t op operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. it is possible to remove vdd while maintaining vdd_io without blocking the communication busses. in this condition the measurement chain is powered off. 3. refer to table 26 for the odr value and configuration. mechanical and electrical specifications lis3de 12/46 docid023719 rev 3 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and t op . figure 3. spi slave timing diagram note: values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both the input and output ports. table 6. spi slave timing values symbol parameter value ( 1 ) unit min. max. t c(spc) spi clock cycle 100 ns f c(spc) spi clock frequency 10 mhz t su(cs) cs setup time 6 ns t h(cs) cs hold time 8 t su(si) sdi input setup time 5 t h(si) sdi input hold time 15 t v(so) sdo valid output time 50 t h(so ) sdo output hold time 9 t dis(so) sdo output disable time 50 6 3 & & 6 6 ' , 6 ' 2 w v x & 6 w y 6 2 w k 6 2 w k 6 , w v x 6 , w k & 6 w g l v 6 2 w f 6 3 & 0 6 % , 1 0 6 % 2 8 7 / 6 % 2 8 7 / 6 % , 1 $ 0 y docid023719 rev 3 13/46 lis3de mechanical and electrical specifications 46 2.4.2 i 2 c - inter-ic control interface subject to general operating conditions for vdd and t op . figure 4. i 2 c slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. table 7. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0.01 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b ( 2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 2. c b = total capacitance of one bus line, in pf. sda scl t f(sda) t su(sp) t w(scll) t su(sda) t r(sda) t su(sr) t h(st) t w(sclh) t h(sda) t r(scl) t f(scl) t w(sp:sr) start repeated start stop start am07229v1 mechanical and electrical specifications lis3de 14/46 docid023719 rev 3 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v. table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo, sdo/sa0) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 2.5 v) 3000 for 0.5 ms g 10000 for 0.1 ms g a unp acceleration (any axis, unpowered) 3000 for 0.5 ms g 10000 for 0.1 ms g t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 2 (hbm) kv this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part. docid023719 rev 3 15/46 lis3de terminology and functionality 46 3 terminology and functionality 3.1 terminology 3.1.1 sensitivity sensitivity describes the gain of the sensor and can be determined, for example, by applying 1 g acceleration to it. as the sensor can measure dc accelerations, this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and also time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 3.1.2 zero- g level zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady-state on a horizontal surface measures 0 g on the x-axis and 0 g on the y-axis whereas the z-axis measures 1 g . the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as two?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is, to some extent, a result of stress to the mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero- g level change vs. temperature?. the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a population of sensors. 3.2 functionality 3.2.1 normal mode, low-power mode the lis3de provides two different operating modes: normal mode and low-power mode . table 9 summarizes how to select the operating mode. 3.2.2 self-test the self-test allows the sensor functionality to be checked without moving it. the self-test function is off when the self-test bit (st) is programmed to ?0?. when the self-test bit is programmed to ?1?, an actuation force is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs exhibit a change in their dc levels which are related to the selected full scale through the device sensitivity. table 9. operating mode selection ctrl_reg1 [3] (lpen bit) operating mode 1 low-power mode 0 normal mode terminology and functionality lis3de 16/46 docid023719 rev 3 when the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test- force. if the output signals change within the amplitude specified in table 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 3.2.3 6d / 4d orientation detection the lis3de includes 6d / 4d orientation detection. 6d / 4d orientation recognition : in this configuration the interrupt is generated when the device is stable in a known direction. in 4d configuration z-axis position detection is disabled. 3.2.4 sleep-to-wake and return-to-sleep functions the lis3de can be programmed to automatically switch to low-power mode upon recognition of a determined event. once the event condition is over, the device returns to the preset normal mode. to enable this function, the desired threshold value must be stored in the act_ths (3eh) registers, while the duration value must be written in the act_dur (3fh) register. when the acceleration, which is internally high-pass filtered, becomes lower than the threshold value on all of the three axes, the device automatically switches to low-power mode (10 hz odr). during this condition, the odrx bits and lpen bit inside ctrl_reg1 (20h) are not considered. once the acceleration rises above the threshold (at least on one axis), the system restores the operating mode and odrs as per the ctrl_reg1 (20h) and ctrl_reg4 (23h) settings. 3.3 sensing element a proprietary process is used to create a surface micro-machined accelerometer. the technology allows processing suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. to be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid the moving parts from being blocked during the molding phase of the plastic encapsulation. when an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. at steady-state the nominal value of the capacitors are a few pf and when an acceleration is applied, the maximum variation of the capacitive load is in the ff range. docid023719 rev 3 17/46 lis3de terminology and functionality 46 3.4 ic interface the complete measurement chain is made up of a low-noise capacitive amplifier which converts the capacitive unbalancing of the mems sensor into an analog voltage using an analog-to-digital converter. the acceleration data may be accessed through an i 2 c/spi interface, therefore making the device particularly suitable for direct interfacing with a microcontroller. the lis3de features a data-ready signal (drdy) which indicates when a new set of measured acceleration data is available, therefore simplifying data synchronization in the digital system that uses the device. the lis3de may also be configured to generate an inertial wakeup and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. both free-fall and wakeup can be available simultaneously on two different pins. 3.5 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero- g level (tyoff). the trimming values are stored inside the device in non-volatile memory. any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. this allows the device to be used without further calibration. 3.6 fifo the lis3de contains a 32-level fifo for each of the three output channels, x, y and z. buffered output allows 4 operation modes: fifo, stream, stream-to-fifo and bypass. where fifo bypass mode is activated fifo is not operating and remains empty. in fifo mode, data from acceleration detection on the x-, y-, and z-axis measurements are stored in fifo. 3.7 auxiliary adc the lis3de contains an auxiliary 10-bit adc with 3 separate dedicated inputs. 3.8 temperature sensor the lis3de is equipped with an internal temperature sensor. temperature data can be enabled by setting the temp_en bit of the temp_cfg_reg (1fh) register to ?1?. when the auxiliary adc and temperature sensor are enabled, the third channel of the adc is used to digitize the temperature sensor output. to retrieve the temperature sensor data, the bdu bit on ctrl_reg4 (23h) must be set to ?1?. both the out_adc3_h and out_adc3_l registers must be read. temperature data is stored inside out_adc3_h as two?s complement data, in 8-bit format, left-justified. application hints lis3de 18/46 docid023719 rev 3 4 application hints figure 5. lis3de electrical connections the device core is supplied through the vdd line while the i/o pads are supplied through the vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f aluminum) should be placed as near as possible to pin 14 of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 5 ). it is possible to remove vdd maintaining vdd_io without blocking the communication bus, in this condition the measurement chain is powered off. the functionality of the device and the measured acceleration data is selectable and accessible through the i 2 c or spi interfaces. when using the i 2 c, cs must be tied high. adc1, adc2 and adc3, if not used, can be left floating or kept connected to vdd or gnd. the functions, the threshold and the timing of the two interrupt pins (int1 and int2) can be completely programmed by the user through the i 2 c/spi interface. 4.1 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standards. it is qualified for soldering heat resistance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www .st.com . cs 10 f vdd 100 nf gnd vdd_io sdo/sao sda/sdi/sdo int1 scl/spc digital signal from/to signal controller. signal levels are defined by proper selection of vdd_io 1 5 8 13 top view 6 9 14 16 9 5 int2 adc2 adc1 adc3 vdd_io rpu rpu pull-up to be added when i2c interface is used am14757v1 docid023719 rev 3 19/46 lis3de digital main blocks 46 5 digital main blocks 5.1 fifo the lis3de embeds a 32-level data fifo for each of the three output channels, x, y and z. this allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. in order to enable the fifo buffer, the fifo_en bit in ctrl_reg5 (24h) must be set to ?1?. this buffer can work according to four different modes: bypass mode, fifo mode, stream mode and stream-to-fifo mode. each mode is selected by the fm [1:0] bits in fifo_ctrl_reg (2eh) . programmable fifo watermark level, fifo empty or fifo overrun events can be enabled to generate dedicated interrupts on the int1 pin (configuration through ctrl_reg3 (22h) ). fifo_src_reg (empty) is equal to ?1? when all fifo samples are ready and fifo is empty. fifo_src_reg (wtm) goes to ?1? if a new data is written in the buffer and fifo_src_reg (fss [4:0]) is greater than or equal to fifo_ctrl_reg (fth [4:0]). fifo_src_reg (wtm) goes to ?0? if reading x, y, z data slot from fifo and fifo_src_reg (fss [4:0]) is less than or equal to fifo_ctrl_reg (fth [4:0]). fifo_src_reg (ovrn_fifo) is equal to ?1? if a fifo slot is overwritten. 5.1.1 bypass mode in bypass mode the fifo is not operational and for this reason it remains empty. for each channel only the first address is used. the remaining fifo levels are empty. bypass mode must be used in order to reset the fifo buffer when a different mode is operating (i.e. fifo mode). 5.1.2 fifo mode in fifo mode, the buffer continues filling data from the x, y and z accelerometer channels until it is full (32 samples set stored). when the fifo is full, it stops collecting data from the input channels and the fifo content remains unchanged. an overrun interrupt can be enabled, int1_overrun = '1' in the ctrl_reg3 (22h) register, in order to be raised when the fifo stops collecting data. when overrun interrupt occurs, the first data has been overwritten and the fifo stops collecting data from the input channels. at the end of the reading procedure it is necessary to exit bypass mode in order to reset the fifo content. after this reset command, it is possible to restart fifo mode just by selecting the fifo mode configuration (fm bits) in register fifo_ctrl_reg (2eh) . 5.1.3 stream mode in stream mode the fifo continues filling data from x, y, and z accelerometer channels, when the buffer is full (32 samples set stored) the fifo buffer index restarts from the beginning and older data is replaced by the current. the oldest values continue to be overwritten until a read operation frees fifo slots. digital main blocks lis3de 20/46 docid023719 rev 3 an overrun interrupt can be enabled, int1_overrun = '1' in the ctrl_reg3 (22h) register, in order to read the entire fifo content at once. if, in the application, it is mandatory not to lose data and it is not possible to read at least one sample for each axis within one odr period, a watermark interrupt can be enabled in order to read partially the fifo and leave memory slots free for incoming data. setting the fth [4:0] bit in the fifo_ctrl_reg (2eh) register to value n, the number of x, y and z data samples that should be read at the watermark interrupt rising is up to (n+1). 5.1.4 stream-to-fifo mode in stream-to-fifo mode, data from the x, y and z accelerometer channels are collected in a combination of stream mode and fifo mode; the fifo buffer starts operating in stream mode and switches to fifo mode when the selected interrupt occurs. the fifo operating mode changes according to the int1 pin value if the tr bit is set to ?0? in the fifo_ctrl_reg (2eh) register or the int2 pin value if the tr bit is set to ?1? in the fifo_ctrl_reg (2eh) register. when the interrupt pin is selected and the interrupt event is configured on the related pin, the fifo operates in stream mode if the pin value is equal to ?0? and it operates in fifo mode if the pin value is equal to ?1?. the switch mode is dynamically performed according to the pin value. stream-to-fifo can be used in order to analyze the sample history that generated an interrupt; the standard operation is to read fifo content when fifo mode is triggered and the fifo buffer is full and stopped. 5.1.5 retrieving data from fifo fifo reads must start from register 28h. fifo x, y and z data are read from out_x (29h) , out_y (2bh) and out_z (2dh) . when the fifo is in stream, stream-to-fifo or fifo mode, a read operation to the out_x (29h) , out_y (2bh) and out_z (2dh) registers provides the data stored in the fifo. each time data is read from the fifo, the oldest x, y and z data are placed in the out_x (29h) , out_y (2bh) and out_z (2dh) registers and both single read and read_burst (d) operations can be used. d. the read address is automatically updated by the device and rolls back to 0x28 when register 0x2d is reached. in order to read all fifo levels in a multiple bytes read, 196 bytes (6 output registers by 32 levels) must be read. fifo reads must start from register 0x28 for output update and 0x2d for fifo pointer update. docid023719 rev 3 21/46 lis3de digital interfaces 46 6 digital interfaces the registers embedded inside the lis3de may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, the cs line must be tied high (i.e. connected to vdd_io). 6.1 i 2 c serial interface the lis3de i 2 c is a bus slave. the i 2 c is employed to write data into registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus; the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both lines must be connected to vdd_io through an external pull-up resistor. when the bus is free, both lines are high. the i 2 c interface is compliant with fast mode (400 khz) i 2 c standards as well as with normal mode. table 10. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl spc i 2 c serial clock (scl) spi serial port clock (spc) sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sa0 sdo i 2 c least significant bit of the device address (sa0) spi serial data output (sdo) table 11. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master digital interfaces lis3de 22/46 docid023719 rev 3 6.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high-to-low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the lis3de is 010100xb. the sdo / sa0 pad can be used to modify the least significant bit of the device address. if the sa0 pad is connected to a voltage supply, lsb is ?1? (address 0101001b) or, if the sa0 pad is connected to ground, the lsb value is ?0? (address 0101000b). this solution permits two different accelerometers to be connected and addressed to the same i 2 c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the lis3de behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-address (sub) is transmitted: the 7 lsb represent the actual register address while the msb enables address auto increment. if the msb of the sub field is ?1?, the sub (register address) is automatically increased to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write), the master transmits to the slave with direction unchanged. table 12 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 12. sad+read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 010100 0 1 01010001 (51h) write 010100 0 0 01010000 (50h) read 010100 1 1 01010011 (53h) write 010100 1 0 01010010 (52h) table 13. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak docid023719 rev 3 23/46 lis3de digital interfaces 46 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low-to-high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of the first register to be read. in the presented communication format, mak is master acknowledge and nmak is no master acknowledge. 6.2 spi bus interface the lis3de spi is a bus slave. the spi allows reading from and writing to the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . table 14. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 15. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 16. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data digital interfaces lis3de 24/46 docid023719 rev 3 figure 6. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. these lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in the case of multiple read/write bytes. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23,...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : r w bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip drives sdo at the start of bit 8. bit 1 : m s bit. when 0, the address remains unchanged in multiple read/write commands. when 1, the address is auto incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods are added. when the m s bit is ?0?, the address used to read/write data remains the same for every block. when the m s bit is ?1?, the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. 6.2.1 spi read figure 7. spi read protocol cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 ms cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms docid023719 rev 3 25/46 lis3de digital interfaces 46 the spi read command is performed with 16 clock pulses. multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1 : m s bit. when 0, does not increment the address; when 1, increments the address in multiple reads. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). bit 16-... : data do(...-8). further data in a multiple byte read. figure 8. multiple byte spi read protocol (2-byte example) 6.2.2 spi write figure 9. spi write protocol the spi write command is performed with 16 clock pulses. the multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 : m s bit. when 0, does not increment the address; when 1, increments the address in multiple writes. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writes. cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ms cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ms digital interfaces lis3de 26/46 docid023719 rev 3 figure 10. multiple byte spi write protocol (2-byte example) 6.2.3 spi read in 3-wire mode 3-wire mode is entered by setting the sim (spi serial interface mode selection) bit to ?1? in ctrl_reg4. figure 11. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : m s bit. when 0, does not increment the address; when 1, increments the address in multiple reads. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). the multiple read command is also available in 3-wire mode. cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ms cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms docid023719 rev 3 27/46 lis3de register mapping 46 7 register mapping table 17 provides a list of the 8-bit registers embedded in the device and the corresponding addresses. table 17. register address map name type register address default comment hex binary reserved (do not modify) 00 - 06 reserved status_reg_aux r 07 000 0111 out_adc1_l r 08 000 1000 output out_adc1_h r 09 000 1001 output out_adc2_l r 0a 000 1010 output out_adc2_h r 0b 000 1011 output out_adc3_l r 0c 000 1100 output out_adc3_h r 0d 000 1101 output int_counter_reg r 0e 000 1110 who_am_i r 0f 000 1111 00110011 dummy register reserved (do not modify) 10 - 1e reserved temp_cfg_reg rw 1f 001 1111 ctrl_reg1 rw 20 010 0000 00000111 ctrl_reg2 rw 21 010 0001 00000000 ctrl_reg3 rw 22 010 0010 00000000 ctrl_reg4 rw 23 010 0011 00000000 ctrl_reg5 rw 24 010 0100 00000000 ctrl_reg6 rw 25 010 0101 00000000 reference rw 26 010 0110 00000000 status_reg2 r 27 010 0111 00000000 reserved (do not modify) - 28 010 1000 00000000 reserved out_x r 29 010 1001 output reserved (do not modify) - 2a 010 1010 00000000 reserved out_y r 2b 010 1011 output reserved (do not modify) r 2c 010 1100 00000000 reserved out_z r 2d 010 1101 output fifo_ctrl_reg rw 2e 010 1110 00000000 fifo_src_reg r 2f 010 1111 ig1_cfg rw 30 011 0000 00000000 register mapping lis3de 28/46 docid023719 rev 3 registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. ig1_source r 31 011 0001 00000000 ig1_ths rw 32 011 0010 00000000 ig1_duration rw 33 011 0011 00000000 ig2_cfg rw 34 011 0100 00000000 ig2_source r 35 011 0101 00000000 ig2_ths rw 36 011 0110 00000000 ig2_duration rw 37 011 0111 00000000 click_cfg rw 38 011 1000 00000000 click_src r 39 011 1001 00000000 click_ths rw 3a 011 1010 00000000 time_limit rw 3b 011 1011 00000000 time_latency rw 3c 011 1100 00000000 time_window rw 3d 011 1101 00000000 act_ths rw 3e 011 1110 00000000 act_dur rw 3f 011 1111 00000000 table 17. register address map (continued) name type register address default comment hex binary docid023719 rev 3 29/46 lis3de register description 46 8 register description 8.1 status_reg_aux (07h) 8.2 out_adc1_l (08h), out_adc1_h (09h) acceleration data - auxiliary adc1 data. the value is expressed in two?s complement. 8.3 out_adc2_l (0ah), out_adc2_h (0bh) acceleration data - auxiliary adc2 data. the value is expressed in two?s complement. 8.4 out_adc3_l (0ch), out_adc3_h (0dh) acceleration or temperature sensor data - auxiliary adc3 data. the value is expressed in 2?s complement. table 18. status_reg_aux register 321or 3or 2or 1or 321da 3da 2da 1da table 19. status_reg_aux register description 321or 1, 2 and 3-channel data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous set) 3or 3 rd channel data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the 3 rd adc channel has overwritten the previous data) 2or 2 nd channel data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the 2 nd adc channel has overwritten the previous data) 1or 1 st channel data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the 1 st adc channel has overwritten the previous data) 321da 1 st , 2 nd and 3 rd channel new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) 3da 3 rd channel new data available. default value: 0 (0: new data for the 3 rd adc channel is not yet available; 1: new data for the 3 rd adc channel is available) 2da 2 nd channel new data available. default value: 0 (0: new data for the 2 nd adc channel is not yet available; 1: new data for the 2 nd adc channel is available) 1da 1 st channel new data available. default value: 0 (0: new data for the 1 st adc channel is not yet available; 1: new data for the 1 st adc channel is available) register description lis3de 30/46 docid023719 rev 3 8.5 int_counter_reg (0eh) int2 pin counter. this register can be reset by reading the reference (26h) register. 8.6 who_am_i (0fh) device identification register. 8.7 temp_cfg_reg (1fh) 8.8 ctrl_reg1 (20h) table 20. int_counter_reg register ic7 ic6 ic5 ic4 ic3 ic2 ic1 ic0 table 21. who_am_i register 00110011 table 22. temp_cfg_reg register adc_pd temp_en 0 00000 table 23. temp_cfg_reg register description adc_pd adc enable. default value: 0 (0: adc disabled; 1: adc enabled) temp_en temperature sensor (t) enable. default value: 0 (0: t disabled; 1: t enabled) table 24. ctrl_reg1 register odr3 odr2 odr1 odr0 lpen zen yen xen table 25. ctrl_reg1 register description odr [3:0] data rate selection. default value: 00 (0000: 50 hz; others: refer to table 26 )3 lpen low-power mode enable. default value: 0 (0: normal mode, 1: low-power mode) zen z-axis enable. default value: 1 (0: z-axis disabled; 1: z-axis enabled) yen y-axis enable. default value: 1 (0: y-axis disabled; 1: y-axis enabled) xen x-axis enable. default value: 1 (0: x-axis disabled; 1: x-axis enabled) docid023719 rev 3 31/46 lis3de register description 46 odr [3:0] is used to set power mode and odr selection. the following table provides all frequencies resulting from a combination of odr [3:0]. 8.9 ctrl_reg2 (21h) table 26. data rate configuration odr3 odr2 odr1 odr0 power mode selection 0000 power-down mode 0001 normal / low-power mode (1 hz) 0010 normal / low-power mode (10 hz) 0011 normal / low-power mode (25 hz) 0100 normal / low-power mode (50 hz) 0101 normal / low-power mode (100 hz) 0110 normal / low-power mode (200 hz) 0111 normal / low-power mode (400 hz) 1000 low-power mode (1.6 khz) 1001 normal (1.344 khz) / low-power mode (5.376 khz) table 27. ctrl_reg2 register hpm1 hpm0 hpcf2 hpcf1 fds hpclick hpis2 hpis1 table 28. ctrl_reg2 register description hpm [1:0] high-pass filter mode selection. default value: 00 refer to table 29 hpcf [2:1] high-pass filter cutoff frequency selection fds filtered data selection. default value: 0 (0: internal filter bypassed; data from internal filter sent to output register and fifo) hpclick high-pass filter enabled for click function. (0: filter bypassed; 1: filter enabled) hpis2 high-pass filter enabled for ig2 (0: filter bypassed; 1: filter enabled) hpis1 high-pass filter enabled for ig1 (0: filter bypassed; 1: filter enabled) table 29. high-pass filter mode configuration hpm1 hpm0 high pass filter mode 0 0 normal mode (reset by reading the register) 0 1 reference signal for filtering 1 0 normal mode 1 1 auto-reset on interrupt event register description lis3de 32/46 docid023719 rev 3 8.10 ctrl_reg3 (22h) 8.11 ctrl_reg4 (23h) table 30. ctrl_reg3 register int1_ click int1_ig1 int1_ig2 int1_ drdy1 int1_ drdy2 int1_ wtm int1_ overrun -- table 31. ctrl_reg3 register description int1_click click interrupt on int1. default value 0 (0: disable; 1: enable) int1_ig1 ig1 interrupt generator 1 on int1. default value 0 (0: disable; 1: enable) int1_ig2 ig2 interrupt generator 2 on int1. default value 0 (0: disable; 1: enable) int1_drdy1 drdy1 interrupt on int1. default value 0 (0: disable; 1: enable) int1_drdy2 drdy2 interrupt on int1. default value 0 (0: disable; 1: enable) int1_wtm fifo watermark interrupt on int1. default value 0 (0: disable; 1: enable) int1_overrun fifo overrun interrupt on int1. default value 0 (0: disable; 1: enable) table 32. ctrl_reg4 register bdu - fs1 fs0 - st1 st0 sim table 33. ctrl_reg4 register description bdu block data update. default value: 0 (0: continuous update. for linear acceleration data output this bit must be set to 0; 1: this bit must be set to 1 for temperature sensor reading only) fs [1:0] full scale selection. default value: 00 (00: 2 g ; 01: 4 g ; 10: 8 g ; 11: 16 g ) st [1:0] self-test enable. default value: 00 (00: self-test disabled; other: see table 34 ) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface) table 34. self-test mode configuration st1 st0 self-test mode 0 0 normal mode 0 1 self-test 0 1 0 self-test 1 11-- docid023719 rev 3 33/46 lis3de register description 46 8.12 ctrl_reg5 (24h) 8.13 ctrl_reg6 (25h) table 35. ctrl_reg5 register boot fifo_en -- -- lir_ig1 d4d_ig1 lir_ig2 d4d_ig2 table 36. ctrl_reg5 register description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) fifo_en fifo enable. default value: 0 (0: fifo disable; 1: fifo enable) lir_ig1 latch interrupt request on ig1_source register, with ig1_source register cleared by reading ig1_source itself. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) d4d_ig1 4d enable: 4d detection is enabled on int1 when 6d bit on ig1_cfg is set to ?1? lir_ig2 latch interrupt request on ig2_source register, with ig2_source register cleared by reading ig2_source itself. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) d4d_ig2 4d enable: 4d detection is enabled on interrupt 2 generator when 6d bit on ig2_cfg is set to ?1? table 37. ctrl_reg6 register int2_click int2_ig1 int2_ig2 int2_boot int2_act - h_lactive - table 38. ctrl_reg6 register description int2_click click interrupt on int2 pin. default value: 0 (0: disable; 1: enable) int2_ig1 interrupt generator 1 enabled on int2 pin. default value: 0 (0: function disable; 1: function enable) int2_ig2 interrupt generator 2 enabled on int2 pin. default value: 0 (0: function disable; 1: function enable) int2_boot boot on int2 pin enable. default value: 0 (0: disable; 1: enable) int2_act ?sleep-to-wake? / ?return-to-sleep? function interrupt enable on int2 pin. default value: 0 (0: disable; 1: enable) h_lactive interrupt active value. default value: 0 (0: interrupt active high; 1: interrupt active low) register description lis3de 34/46 docid023719 rev 3 8.14 reference (26h) 8.15 status_reg2 (27h) 8.16 out_x (29h) x-axis acceleration data. the value is expressed in two?s complement with 8-bit data representation left-justified. table 39. reference register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 40. reference register description ref [7:0] reference value for interrupt generation. default value: 0000 0000 table 41. status_reg2 register zyxor zor yor xor zyxda zda yda xda table 42. status_reg2 register description zyxor x-, y- and z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous set) zor z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis has overwritten the previous data) yor y-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xor x-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x-, y- and z-axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z-axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y-axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) xda x-axis new data available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available) docid023719 rev 3 35/46 lis3de register description 46 8.17 out_y (2bh) y-axis acceleration data. the value is expressed in two?s complement with 8-bit data representation left-justified. 8.18 out_z (2dh) z-axis acceleration data. the value is expressed in two?s complement with 8-bit data representation left-justified. 8.19 fifo_ctrl_reg (2eh) 8.20 fifo_src_reg (2fh) table 43. fifo_ctrl_reg register fm1 fm0 tr fth4 fth3 fth2 fth1 fth0 table 44. fifo_ctrl_reg register description fm [1:0] fifo mode selection. default value: 00 (see table 45 ) tr trigger selection. default value: 0 0: trigger event linked to trigger signal on int1 1: trigger event linked to trigger signal on int2 fth [4:0] default value: 0 table 45. fifo mode configuration fm1 fm0 self-test mode 0 0 bypass mode 0 1 fifo mode 1 0 stream mode 1 1 stream-to-fifo mode table 46. fifo_src_reg register wtm ovrn_fifo empty fss4 fss3 fss2 fss1 fss0 table 47. fifo_src_reg register description wtm wtm bit is set high when fifo content exceeds watermark level ovrn_fifo ovrn bit is set high when fifo buffer is full; this means that the fifo buffer contains 32 unread samples. at the following odr a new sample set replaces the oldest fifo value. the ovrn bit is set to 0 when the first sample set has been read empty empty flag is set high when all fifo samples have been read and fifo is empty fss [4:0] fss [4:0] field always contains the current number of unread samples stored in the fifo buffer. when fifo is enabled, this value increases at odr frequency until the buffer is full, whereas, it decreases every time one sample set is retrieved from fifo register description lis3de 36/46 docid023719 rev 3 8.21 ig1_cfg (30h) the content of this register is loaded at boot. a write operation to this address is possible only after system boot. the difference between aoi-6d = ?01? and aoi-6d = ?11?. aoi-6d = ?01? is movement recognition. an interrupt is generated when the orientation moves from an unknown zone to a known zone. the interrupt signal remains for a duration odr. aoi-6d = ?11? is direction recognition. an interrupt is generated when the orientation is inside a known zone. the interrupt signal remains until the orientation is within the zone. table 48. ig1_cfg register aoi 6d zhie/ zupe zlie/ zdowne yhie/ yupe ylie/ ydowne xhie/ xupe xlie/ xdowne table 49. ig1_cfg register description aoi and/or combination of interrupt events. default value: 0 (refer to table 50 ) 6d 6-direction detection function enabled. default value: 0 (refer to table 50 ) zhie/ zupe enable interrupt generation on z high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) zlie/ zdowne enable interrupt generation on z low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) yhie/ yupe enable interrupt generation on y high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) ylie/ ydowne enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) xhie/ xupe enable interrupt generation on x high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) xlie/ xdowne enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) table 50. interrupt mode aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 1 1 6-direction position recognition docid023719 rev 3 37/46 lis3de register description 46 8.22 ig1_source (31h) interrupt 1 source register. read-only register. reading at this address clears the ig1_source ia bit (and the interrupt signal on the int1 pin) and allows data in the ig1_source register to be refreshed if the latched option was chosen. 8.23 ig1_ths (32h) 8.24 ig1_duration (33h) d [6:0] bits set the minimum duration of the interrupt 1 event to be recognized. duration steps and maximum values depend on the odr chosen. table 51. ig1_source register 0 ia zhzlyhylxhxl table 52. ig1_source register description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 53. ig1_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 54. ig1_ths register description ths [6:0] interrupt 1 threshold. default value: 000 0000 table 55. ig1_duration register 0 d6d5d4d3d2d1d0 table 56. ig1_duration register description d [6:0] duration value. default value: 000 0000 register description lis3de 38/46 docid023719 rev 3 8.25 ig2_cfg (34h) the content of this register is loaded at boot. a write operation to this address is possible only after system boot. the difference between aoi-6d = ?01? and aoi-6d = ?11?. aoi-6d = ?01? is movement recognition. an interrupt is generated when the orientation moves from an unknown zone to a known zone. the interrupt signal remains for a duration odr. aoi-6d = ?11? is direction recognition. an interrupt is generated when orientation is within a known zone. the interrupt signal remains while the orientation is within this zone. table 57. ig2_cfg register aoi 6d zhie zlie yhie ylie xhie xlie table 58. ig2_cfg register description aoi and/or combination of interrupt events. default value: 0 (refer to table 59: interrupt mode ) 6d 6-direction detection function enabled. default value: 0 (refer to table 59: interrupt mode ) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 59. interrupt mode aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 1 1 6-direction position recognition docid023719 rev 3 39/46 lis3de register description 46 8.26 ig2_source (35h) interrupt 2 source register. read-only register. reading at this address clears the ig2_source ia bit (and the interrupt signal on the int2 pin) and allows data in the ig2_source register to be refreshed if the latched option was chosen. 8.27 ig2_ths (36h) 8.28 ig2_duration (37h) the d [6:0] bits set the minimum duration of the interrupt 2 event to be recognized. duration time steps and maximum values depend on the odr chosen. table 60. ig2_source register 0 ia zhzlyhylxhxl table 61. ig2_source register description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 62. ig2_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 63. ig2_ths register description ths[6:0] interrupt 1 threshold. default value: 000 0000 table 64. ig2_duration register 0 d6d5d4d3d2d1d0 table 65. ig2_duration register description d [6:0] duration value. default value: 000 0000 register description lis3de 40/46 docid023719 rev 3 8.29 click_cfg (38h) 8.30 click_src (39h) table 66. click_cfg register -- -- zd zs yd ys xd xs table 67. click_cfg register description zd enable interrupt double-click on z-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zs enable interrupt single-click on z-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) yd enable interrupt double-click on y-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ys enable interrupt single-click on y-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xd enable interrupt double-click on x-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xs enable interrupt single-click on x-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) table 68. click_src register - ia dclick sclick sign z y x table 69. click_src register description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) dclick double-click enable. default value: 0 (0: double-click detection disable, 1: double-click detection enable) sclick single-click enable. default value: 0 (0: single-click detection disable, 1: single-click detection enable) sign click sign. 0: positive detection, 1: negative detection z z click detection. default value: 0 (0: no interrupt, 1: z high event has occurred) y y click detection. default value: 0 (0: no interrupt, 1: y high event has occurred) x x click detection. default value: 0 (0: no interrupt, 1: x high event has occurred) docid023719 rev 3 41/46 lis3de register description 46 8.31 click_ths (3ah) 8.32 time_limit (3bh) 8.33 time_latency (3ch) 8.34 time_window (3dh) table 70. click_ths register lir ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 71. click_ths register description lir latch interrupt request on click_src register, with click_src register cleared by reading click_src itself. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) ths [6:0] click threshold. default value: 000 0000 table 72. time_limit register - tli6 tli5 tli4 tli3 tli2 tli1 tli0 table 73. time_limit register description tli [6:0] click time limit. default value: 000 0000 table 74. time_latency register tla7 tla6 tla5 tla4 tla3 tla2 tla1 tla0 table 75. time_latency register description tla [7:0] double-click time latency. default value: 0000 0000 table 76. time_window register tw7 tw6 tw5 tw4 tw3 tw2 tw1 tw0 table 77. time_window register description tw [7:0] double-click time window. default value: 0000 0000 register description lis3de 42/46 docid023719 rev 3 8.35 act_ths (3eh) 8.36 act_dur (3fh) table 78. act_ths register -- acth6 acth5 acth4 acth3 acth2 acth1 acth0 table 79. act_ths register description acth [6:0] sleep-to-wake, return-to-sleep activation threshold 1lsb = 16 m g @ 2 g fs table 80. act_dur register actd7 actd6 actd5 actd4 actd3 actd2 actd1 actd0 table 81. act_dur register description actd [7:0] sleep-to-wake, return-to-sleep duration dur = (act_dur + 1)*8/odr docid023719 rev 3 43/46 lis3de package information 46 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. package information lis3de 44/46 docid023719 rev 3 figure 12. lga-16: drawing table 82. lga-16: mechanical data dim. mm min. typ. max. a1 1 a2 0.785 a3 0.2 d1 2.85 3 3.15 e1 2.85 3 3.15 l1 1 1.06 l2 2 2.06 n1 0.5 n2 1 m 0.04 0.1 0.16 p1 0.875 p2 1.275 t1 0.29 0.35 0.41 t2 0.19 0.25 0.31 d 0.15 k 0.05 7983231 docid023719 rev 3 45/46 lis3de revision history 46 10 revision history table 83. document revision history date revision changes 21-sep-2012 1 initial release. 30-jan-2013 2 document status promoted from preliminary to production data. 19-jun-2014 3 updated trigger mode to stream-to-fifo mode minor textual modifications throughout document. lis3de 46/46 docid023719 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industr y domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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